# Modeling of Combinational Logic Circuits ## Modeling of Combinational Logic Circuits

In this learning, we are dealing with Modeling of Combinational Logic Circuits. A combinational circuit is a special-purpose circuitry, consists of an interconnection of logic gates. The outputs at any instant of time are dependent on the present combination of inputs only. A block diagram of a combinational circuit is below:

The ‘n’ input binary variables come from external sources. The ‘m’ output variables are produced by the internal combinational logic circuit and go to an external destination. Each input and output variables exist physically as an analog signal whose values are interpreted to be a binary signal that represents logic ‘1’ and logic ‘0′.

For ‘n’ input variables, there are 2^n possible combinations of binary inputs. In other words, each output function is expressed in terms of the ‘n’ input variable. A combinational circuit can also be specified by a truth table. It lists the output for each combination of input variables.

The combinational circuits are further divided into Arithmetic and Non-Arithmetic Circuits. As the name suggests the former circuit performs the arithmetic. In this article, we will discuss all the popular arithmetic combinational circuits available in digital electronics.

The half adder is an arithmetic circuit used to perform the addition of two single bits. The two input variables to the half adder designate the augend and addend bits. The yields are the sum and carry bits. Listed below is the truth table of half adder.

Let A and B are the two input variables, and sum (S) and carry (C) are the two output variables then the simplified Boolean functions for the two outputs can be obtained directly from the truth table.
The logical expressions for sum and carry are:
S=A’B+AB’= A ⊕ B
C=A.B

From the given expression, a half adder can be realized by using one Ex-OR gate and an AND gate, as shown.

NAND and NOR are universal gates. Hence, a half adder circuit, like most circuitries, can be realized using either of them.

### Design Module

Here, the code is modeled using Gate Level modeling.

``````module ha(s ,c, a, b);
output reg s,c;
input a,b;
xor a1(s, a, b);
and a2(c, a, b);
endmodule``````

### Test- Bench

``````module ha_tb;
reg a,b;
wire s,c;
ha dut(s,c,a,b);
initial
begin
\$monitor( a, b,c,s);
\$dumpfile("dump.vcd");
\$dumpvars;
end
initial
begin
a=0;
b=0;
#100
a=0;
b=1;
#100
a=1;
b=0;
#100
a=1;
b=1;
end
endmodule``````

A full-adder is an arithmetic combinational circuit that performs the sum of three input bits. It consists of three input variables designated by augends, addend and the carry bit. Resultants are the SUM and CARRY.

See also  Counters and Registers: Design and Test-bench Verilog

Let the two input factors are meant by A and B, speak to the two noteworthy bits to be added. C is the carry from previous LSB position. The two yields are Sum (S) and Carry (Cout).
S= A’B’C+A’BC’+ AB’C’+ ABC = A ⊕ B ⊕ C
Cout = AB + BC + CA = AB+ C(A ⊕ B)

A full adder can be modeled using behavioral, gate-level or data flow style. Here, we are using half adders to construct a full adder. In other words, this is the concept of Design Reusability. Below is the diagram for the same.

### Design Module

``````module fa(sum, carry, a, b, c);
output reg sum, carry;
input a, b, c;
wire x,y,z;
ha ha1(x, y, a, b); //instantiation
ha ha2(sum, z, x, c);
or(carry, y, z);
endmodule
module ha(s ,c, a, b);
output reg s,c;
input a,b;
xor a1(s, a, b);
and a2(c, a, b);
endmodule``````

### Test Bench

``````module fa_tb;
reg a, b, c;
wire sum, carry;
fa dut(sum, carry, a, b, c);
initial
begin
a=0; b=0; c=0;
#100 a=0; b=0; c=1;
#100 a=0; b=1; c=0;
#100 a=0; b=1; c=1;
#100 a=1; b=0; c=0;
#100 a=1; b=0; c=1;
#100 a=1; b=1; c=0;
#100 a=1; b=1; c=1;
end
initial
begin
\$monitor( sum, carry, a, b, c);
\$dumpfile("dump.vcd");
\$dumpvars;
end
endmodule``````

In general, we can design an n-bit adder. But as the number of bits increase, the complexity will increase.

Read more: Modeling Basic Gates through Verilog

This is the circuitry of a 16-bit adder. The adder will take two 16- bit data as input, A and B, and it will generate a result, C as output. We shall be looking at one more thing, the process of generation of the status flags.

In many circuits, especially microprocessors, there are some state flags which automatically set or resets after the realization of arithmetic or logical operation. In conclusion, this status flag is an array that consists of a sign, zero, carry and parity bits. The flag will determine the resultant and nature of the operation performed.

The sign flag will ascertain whether the result is negative or positive. After the addition, if the MSB is one, the number turns out to be negative and sign flag sets. Likewise, if MSB is zero, the number is positive, and the flag resets.

The zero flags will determine whether the result is zero or non-zero. If the resultant is 0, the flag will set. The carry flag will determine whether there was a carry out of the addition. The parity flag will tell whether the number of ones in the result is odd or even.

See also  Designing Combinational Circuits through Verilog HDL

### Functionality

Let us try to understand our design module. A and B are 16-bit data to be entered. C will be the output. But because we are considering the status flag here, we will concatenate Carry and C using the concatenation operation. So, if the carry will generate besides it goes into the carry flag.

Here the numbers are represented in two’s complement form. So, in two’s complement representation, the most significant bit of the number indicates the Sign. So, the MSB of the result C that will go into the sign flag. In the code, we are assigning the most significant bit C15 to Sign flag. Like C language, it is possible in Verilog HDL to slice out the array and attach it.

The zero flag will tell whether the result is zero or not. For output to be zero its, all bits ought to zero. In this case, the zero flag will set. To decipher its functionality, considering all bits to be zero, we will use a NOR operation. Oring all the zeros and complementing them, the outcome will be one. Hence flag will set.

EX-NOR gate serves as the equality detector. For the parity flag, we will simply use an ex-nor operator. For even parity, the flag sets and resets for odd. So if we find an even number of ones in the result, the output of the gate will be 1. Hence our function will serve.

### Design Module

``````module 16_bit(carry,sign,zero,parity,C,A,B);
input [15:0] A,B;
output carry,sign,zero,parity;
output [15:0] C;
assign {carry,C}= A+B;
assign sign= C;
assign zero= ~|C;
assign parity= ~^C;
endmodule``````

## Binary Parallel Adder

A binary parallel adder is a combinational digital circuit that adds two binary numbers in parallel form. It comprises of full-adders associated in series, with the yield carry from each adder associated with the input carry of the following adder.

For the addition of n-bit numbers, a chain of n full adders is required, or a chain of the one-half adder and (n-1) full adders are needed. The input to the LSB position is always zero.

For the addition of n-bit numbers, a chain of n full adders is required, or a chain of the one-half adder and (n-1) full adders are needed. The input to the LSB position is always zero.

See also  Designing Sequential Circuits through Verilog

As mentioned above C carry should be 0. The zero is transferred to the input of carry of a first full adder, that is added to the bit present in the next significant place at left. The sum bits are generated from the rightmost place.

The Carry propagated adder is one of the representations of Binary Parallel Adder.

## Carry Propagation Adder

The addition of two binary numbers in parallel implies that all the bits of the input variables are available for computation at the same time. As, in any combinational circuit, the sign must engender through the gates before the yield is accessible in the output terminals. The complete propagation time is equivalent to the propagation delay of average gates in the circuit.

The longest range defers time in an adder is the time it takes the bring to engender through the full adder. Thus, the carry propagation delay is the time between process of carry-in and carry-out. In parallel adder, carry bit propagates from least to the most significant bit in a ripple-like manner. So, it is popularly known as ‘RIPPLE CARRY ADDER.

In ‘n’ bit parallel adder, minimum delay to provide the final result is equal to 2ntpd (where tpd= propagation delay of each gate). That is why parallel adder becomes very slow. To overcome this difficulty, a new type of adder is used, which is called “LOOK AHEAD CARRY ADDER.”

### Design Module

``````module ripple_carry_adder(a, b, sum, carry);
output reg [3:0] sum;
output carry;
input [3:0] a, b;
wire w1,w2,w3;
fulladder f1(a, b, 0, sum, w1);
fulladder f2(a, b, w1, sum, w2);
fulladder f3(a, b, w2, sum, w3);
fulladder f4(a, b, w3, sum, carry);
endmodule
module fulladder(x, y, c, s, co);
input x, y, c;
output reg s, co;
wire x1,x2,x3;
xor G1(x1, x, y);
xor G2(s, x1, c);
and G3(x2, x1, c);
and G4(x3, x, y);
or G5(co, x2, x3);
endmodule``````

### Test Bench

``````module testbench;
reg [3:0] a,b;
wire [3:0]sum;
wire carry;
ripple_carry_adder dut(a, b, sum, carry);
initial
begin
a=4'b0000; b=4'b0101;
#100 a=1010; b=0001;
#100 a=0110; b=0100;
end
initial
begin
\$monitor( sum, carry, a, b);
\$dumpfile("dump.vcd");
\$dumpvars;
end
endmodule``````

## Conclusion

In the write-up “Modeling of Combinational Logic Circuits“, we discuss a few popular arithmetic units of combinational circuits. These circuitries form the basis of Arithmetic and Logic Units(ALUs). In the following article, we will see other important arithmetic circuits.

### 7 thoughts on “Modeling of Combinational Logic Circuits”

1. Thanks for sharing, of great help.

2. Can you tell me the process of the Hong Kong university admission.

3. Really impressed by your writing skills.

4. You seem to be topper of your college

5. 6. 